1. Field of the Invention
The present invention relates to a Power Factor Correction (PFC) Circuit. More particularly, the present invention relates to a new way of managing and controlling an Active PFC System, not by using a classic “Multiplier” concept and its related circuit, but by using an original “Constant Pulse—Proportional Current” (CPPC) conversion concept, embedded via several electronic circuits that have a novel configuration and/or architecture.
Introduction
In the process of transferring AC electrical power from a generator to a load via different converting devices, in addition to the Efficiency, the Power Factor is also a very important parameter.
The Efficiency parameter (Eff=Pout/Pin) provides information about the percentage of the inputted electrical power that has been transferred, by a specific electrical device, to its output load. Usually, the rest of the electrical power, which has not been delivered to the load, is transformed into heat, dissipated by the electrical device's parts.
The Power Factor parameter is not related at all to an electrical device's in/out transfer of the electrical energy (i.e. its efficiency), however it provides information about how well it has managed the “Real Power” absorbed by an electrical device, versus the “Apparent Power” requested by that device from its electrical generator.
The Real Power, defined by the following relation:P(Watts)=[1:T×∫(Vi×li,dt)]is the watts power absorbed by a device from its electrical generator and its value is proportional to the integral of the voltage and current product/time unit.
The Apparent Power (or RMS Power), defined by the following relation:P(VA)=Vrms×Irms is the Volt-Amperes power requested by a device from its electrical generator and its amount's value is proportional to the product of the rms Voltage and the rms Current.
Accordingly, the Power Factor (PF) parameter is defined by the following relation:PF=[1:T×∫(Vi×li,dt)]:(Vrms×Irms);W/VA<1respectively, the Real Power to the Apparent Power (W/VA) ratio.
2. The Related Art
Passive PFC Solutions
The simplest methods to increase PF and lower Total Harmonic Distortion (THD) are the ones using passive components (inductors and capacitors). Usually, the performances of these kinds of “Passive PFC Solutions” are relatively low, just near the “acceptable” limits of the industry standards.
Active PFC Solutions
Better methods of increasing the PF and lowering the THD in a power supply circuit are the ones comprising so called “Active PFC Systems” that include typically an oscillating coil activated by a power MOSFET transistor (inverter circuit), which is controlled by a PFC Controller Circuit.
The PFC Controller Circuit is basically a classic Pulse Width Modulator (PWM) circuit which includes typically, a “Multiplier” and some other multiplier related sub-circuits, necessarily for forcing the power supply's input current shape to follow the input voltage shape (i.e. a sine wave).
Pulse Width Modulation Circuits
FIG. 1A illustrates a Classic PWM Controller (UC384x series) Circuit's Open Loop Laboratory Fixture and the Timing Diagrams related to the high frequency driving control pulses necessary for controlling a power MOSFET's invertors circuit. The main functional blocks of an UC384x are an internal supply and protections block (ISP), a voltage references block (Vref), an output driver block (DRV), a pulse width modulation logic block (PWM Logic), a voltage error amplifier block (VEA), a voltage limiter block (VL), a pulse width modulation Comparator block (C), and an oscillator block (OSC). Eight I/O electrodes: Comp (1), Vfb (2), Is (3), RC (4), GND (5), Output (6), Vcc (7) and REF (8) are connecting the internal functional blocks to the controllers related circuit.
The ISP block supplies and protects all the other internal blocks against over voltages. The Vref block provides high precision (1%) references voltages to the internal and external (via REF electrode 8) circuit. The DRV block is basically a high voltage (20 v) buffer for the “Y” signal outputted by the PWM Logic block.
The main purpose of attaching the PWM Logic block between the PWM Comparator and DRV is to prevent more than one output pulse during one cycle of the OSC.
As the Timing Diagrams of FIG. 1B show, the OSC block provides the PWM Logic block with setting (Set) pulses having the frequency pre-established by a voltage ramp (VR) signal created externally by R3 and C1.
The Set pulse level is 0 (LOW) during the time when R3 is charging C1 (VR voltage level increases slow) and the Set pulse level is 1 (HIGH) during the time when C1 is internally discharged into the OSC block (VR voltage level decreases faster).
Obviously, the Set pulse lasting time is proportional to the value of C1 (as the C1 value increases, a longer discharge time follows).
When S reaches 0 (LOW) logic level (assuming that R is LOW already), the Y output (of the PWM Logic block) switch to 1 (HIGH) logic level. The Y output (and implicitly the main Output (6) electrode) remains at the HIGH logic level until one of the R, S inputs reaches the 1 (HIGH) logic level.
If the R input never switches to 1 (HIGH), then the Output (6) will provide a maximum duty cycle pulse similar, but in opposite phase, to the Set signal.
In order for R to switch to 1 (HIGH) the current sense Is (3) input's voltage level must be higher than the fraction of the Comp (1) voltage level delivered by the VL block (VLo) to the inverting input of the pulse width modulation comparator (C).
Typically, the Comp (1) voltage is resistively divided (⅓) and also limited at a maximum 1V by the VL block, so by buffering the VR-A signal incoming from RC (4) via a NPN transistor Q1 and adjusting its level properly, via the potentiometer P2, a lower maximum duty cycle can be set, in respect to the 1V maximum threshold established at the inverting input of the PWM comparator (C). P2 is able to adjust a maximum duty cycle, at any ratio between 30% and 90% (some of the UC384x controllers' series circuits contain inside an extra sub-circuit for limiting the maximum duty cycle at 50%). If, P2 is connected in series with a current sense resistor to ground, the PWM controller (C) can work in a Current/Voltage mode combination, which provides more stability to the entire circuit.
The minimum duty cycle is provided by VEA when the amount of voltage at Vfb (2) electrode is higher than Vref2 (2.5V+/−1%). R1, R2 and P1 are able to provide a voltage higher than 2.5V, since the REF (8) voltage is 5V (+/−1%).
R4 provides VEA with feedback and stability, R5 acts as a load for the Output (6) electrode and C2, C3 are preventing high frequency oscillations at Vcc (7) and REF (8) electrodes. By adjusting P1, the Output pulse minimum ON time can be decreased, in voltage mode, down to 1-3 μS, depending of the 384×IC manufacturer. The Timing Diagrams of FIG. 1B shows progressively the Output pulse as a function of the Set, VLo, Is and R signals.
In accordance with the above description, the Output pulse starts when Set reaches its (LOW) level, and stops when Reset reaches 1, so the DRV pulse duty cycle is proportional to the VLo signal momentary voltage level, in respect to GND (5). If R remains LOW, then Output pulse goes LOW when the next Set pulse rises (maximum duty cycle). If R remains HIGH or goes LOW after Set switches LOW, then the Output pulse remains LOW (no more Output pulses). The PWM comparator (C), is as fast as the minimum ON time of the Output pulse is short. Unfortunately, being designed as a current mode PWM controller, the existing 384×IC controllers series reaches, in voltage mode of operations (via Q1, as voltage ramp driver) a minimum Output pulse ON time around 1 μS or more, which is too long a time for accurate control at high frequency. For a high performances PFC System, the minimum ON time pulse needed is less than 0.1 μS (preferable 0.01 μS).
Description of a Classic PFC Circuits
FIG. 2 illustrates the most common Active PFC System containing, besides the Alternative Current Generator (Vac), five functional blocks such as a Low Pass Filter (LPF), a Bridge Rectifier (BR), a Power Factor Correction Large Signal Circuit (PFC-LSC), a Complex Load (CL) and a Power Factor Correction Small Signal Circuit (PFC-SSC), which is represented by the Controller Circuit and some extra parts such as Rvin and Rvout, included in a Controller Related Circuit (CRC).
The LPF block design purpose is to protect the input generator Vac from the high frequency noise incoming from the PFC-LSC block and usually contains an input filtrating capacitor Cf1, a symmetrical double coil filter Lf1 and a second filtrating capacitor Cf2. The BR block comprises a bridge of four rectifying diodes (Dr1-DR4) that convert the AC input voltage into a pulse (semi cycles) DC voltage. The CL block contains a bulk capacitor Cb and a resistive load R1. The PFC-LSC block comprises an inductor L1, a diode D1, a capacitor C1, a power MOSFET transistor M1 and some times, an additional snubber circuit including a capacitor Cs, a resistor Rs and a diode Ds. The purpose of this attached Snubber Circuit is to decrease the M1 heat dissipation cumulated at the beginning of it's each OFF cycle. Simply, when M1 switches OFF, its drain voltage increases very fast from zero up to 300-500 v, because of the coil L1 self-inductance (reverse voltage). The capacitor Cs, appearing in parallel to M1 (via Ds), creates a necessary delay (from a few hundred nS up to over one μS, function of Cs and L1 values) to this voltage increasing course. This delay must be long enough for the MOSFET to switch OFF completely, or at least to reduce substantially its drain-source current when M1 drain electrode reaches a significant high voltage (P=V*I). When M1 switches back ON, Cs is discharged into M1 via Rs, which reduces the discharge current.
This snubber circuit just decreases the MOSFET working temperature but does not increase the efficiency of the circuit, because the resistor Rs dissipates in heat about the same electrical energy that has been apparently saved from the M1's OFF switching transit time. The only advantage for attaching this circuit is a lower sized aluminum heat sink and/or a lower working temperature for M1.
The PFC-SSC includes a Multiplier (MULT) block, a Current Error Amplifier (CEA) block, a Voltage Error Amplifier (VEA) block, a PWM Comparator (PWMC) block, a PWM Logic block, an oscillator (OSC) block and a Driver (DRV) block.
As an important observation, except for the Multiplier sub-circuit, all of the other blocks are functional blocks of a typical PFC controller and are also included in the low cost PWM controller.
Five I/O electrodes such as Vins (sensing the Vin+momentary value), Is (sensing the M1 momentary current), DRV (providing the ON/OFF switching control to the gate of M1), Vfb (sensing the “Vo+” momentary amount) and GND are necessary in order for PFC-SSC to be able to control the PFC-LSC block.
When the voltage outputted by Vac is applied to the PFC-LSC through the LPF and BR blocks, the full-wave rectified pulse outputted by BR appears at Vin+ and Vin− (positive polarity at Vin+).
Initially at “Vo+” (in respect to GND), a DC voltage is created, in value slightly lower than the peak input voltage and the input current shape is similarly to the one shown in FIG. 14B.
The PFC-SSC block provides the gate of MOSFET (M1) with a relatively high frequency (30-200 KHz) square wave pulse. M1 remains ON until the current in L1 reaches a specific level, then switching OFF; the energy stored in L1 is then delivered to CL, through D1.
As soon Cb is charged to a higher value than the peak of Vin (boost converter), there is no more direct current between Vac and CL (BR diodes and D1 are reverse polarized) so the input current shape depends of the L1 average current only, which is controlled by the switching cycle of the Controller Circuit via M1.
The Multiplier block “MULT” is designed to control the MOSFET pulse in such a way (by multiplying the VEA signal in a specific ratio, function of “Vin+” level) that the momentary current value in L1 (via M1 circuit to GND) becomes proportional to the momentary AC generator voltage amount.
That forces the input current shape to follow the input voltage shape, in fact which pushes the PF parameter level near 1. The final input current shape may have any form, which means a PF parameter from about 0.9 to 0.999.
Cost vs. Performances
Therefore, a need exists for a Low Cost High Performances Power Factor Correction Circuit which is reliable, efficient, small sized, simple in design, includes a lower parts count and does not require a sophisticated and expensive Multiplier sub-circuit.